module rf (
	              // Outputs
	              read1data, read2data, err,
	              // Inputs
	              clk, rst, read1regsel, read2regsel, writeregsel, writedata, write
	   );

   input clk, rst;
   input [2:0] read1regsel;
   input [2:0] read2regsel;
   input [2:0] writeregsel;
   input [15:0] writedata;
   input        write;
   output [15:0] read1data;
   output [15:0] read2data;
   output        err;


      // your code
    wire [15:0] qa,qb,qc,qd,qe,qf,qg,qh;
    wire [15:0] da,db,dc,dd,de,df,dg,dh;

    mux_16b_8_1 mux_a (
            qa,qb,qc,qd,qe,qf,qg,qh,
            read1regsel, read1data);

    mux_16b_8_1 mux_b (
            qa,qb,qc,qd,qe,qf,qg,qh,
            read2regsel, read2data);

    wire [7:0]  decoder_out;
    wire [7:0]  wren = decoder_out & {8{write}};
    decoder_3_8 decoder (.S(writeregsel),.decoder_out(decoder_out));

    dff16 dff0 (.q(qa), .d(writedata), .clk(clk), .rst(rst), .wr_en(wren[0]));
    dff16 dff1 (.q(qb), .d(writedata), .clk(clk), .rst(rst), .wr_en(wren[1]));
    dff16 dff2 (.q(qc), .d(writedata), .clk(clk), .rst(rst), .wr_en(wren[2]));
    dff16 dff3 (.q(qd), .d(writedata), .clk(clk), .rst(rst), .wr_en(wren[3]));
    dff16 dff4 (.q(qe), .d(writedata), .clk(clk), .rst(rst), .wr_en(wren[4]));
    dff16 dff5 (.q(qf), .d(writedata), .clk(clk), .rst(rst), .wr_en(wren[5]));
    dff16 dff6 (.q(qg), .d(writedata), .clk(clk), .rst(rst), .wr_en(wren[6]));
    dff16 dff7 (.q(qh), .d(writedata), .clk(clk), .rst(rst), .wr_en(wren[7]));


endmodule // rf

